SAN JOSE, CALIF. – Breker Verification Systems has joined RISC-V International (RVI) as a strategic member. Breker will offer its expertise in SoC verification solutions to the RVI working groups.
“As the complexity of RISC-V processors for state-of-the-art systems continues to increase, rigorous commercial verification has become paramount,” remarks Calista Redmond, CEO of RISC-V International, the non-profit organization that maintains RISC-V as a free and open processor instruction set architecture (ISA). “Breker’s proven expertise and insights in this area are invaluable to enable the industry to address these challenges.”
Breker is known for its leadership in test content synthesis that leverages C++ and the Accellera Portable Stimulus Standard (PSS) specification models for UVM and SoC applications. It provides a portfolio of TrekApps that generates high-coverage, optimized tests to address common verification scenarios, including Cache Coherency, Security, Power Domain Management, Packet Generation, and the integration of ARM and RISC-V processors. Breker’s portfolio, in use at many leading semiconductor companies, is directly applicable to RISC-V SoCs, and invaluable to both processor developers driving quality and end-users looking to increase confidence in integrated devices.
“RISC-V International has revolutionized the semiconductor industry, and we are now seeing the result of this in widespread industry activity and at many of our semiconductor customers,” notes David Kelf, Breker’s CEO. “Rigorous, commercial verification is now critical for the ongoing success of RISC-V and Breker is committed to working with the organization to provide such solutions.”
Breker became a member to influence the development of a cache coherency and integration test content platform for RISC-V processor development and end-use verification. With the RISC-V ISA leveraged in greater numbers of advanced, application processors, this type of platform offers critical test functionality for many RISC-V stakeholders.
Breker at Design Automation Conference
Breker will demonstrate its System Coherency Synthesis TrekApp and other solutions at Design Automation Conference (DAC) in Booth #2528 (Second floor) Monday, July 11, through Wednesday, July 13, from 10 a.m. until 6 p.m. at the Moscone West in San Francisco.
