Cadence Design Systems announced the delivery of the Cadence Joules RTL Design Studio, a new solution that provides users with actionable intelligence to accelerate the register transfer level (RTL) design and implementation process. Front-end designers can access digital design analysis and debugging capabilities from a single, unified cockpit, enabling fully optimized RTL design prior to implementation handoff. With this solution, users will also be able to leverage generative AI for RTL design exploration and big data analytics with Cadence’s leading AI portfolio. With Joules RTL Design Studio, users can achieve physical estimates quickly and accurately, unlocking up to 5X productivity and up to 25% quality of results (QoR) improvements in the RTL.
Joules RTL Design Studio expands upon Cadence’s existing Joules RTL Power Solution, addressing all aspects of physical design by adding visibility into power, performance, area, and congestion (PPAC).
In addition, the new tool comes with a host of productivity-enhancing features and benefits, including:
- Provides early PPAC metrics as well as actionable debugging information throughout the design cycle—logical, physical, and production implementation—so engineers can explore “what-if” scenarios and potential resolutions to minimize iterations and improve design outcomes.
- Joules RTL Design Studio shares the same trusted engines as the Innovus Implementation System, Genus Synthesis Solution, and Joules RTL Power Solution, enablingusers to access all analysis and design exploration features from a single GUI for optimal QoR.
- Joules RTL Design Studio has an integration with the generative-AI solution, Cadence Cerebrus Intelligent Chip Explorer, to explore design space scenarios, such as floorplan optimization and frequency versus voltage tradeoffs. Additionally, the Cadence Joint Enterprise Data and AI (JedAI) Platform allows trend and insight analysis across different versions of the RTL or across previous project generations.
- Allowsengineerstorun lint checkers incrementally to rule out data and setup issues up-front, reducing errors and time to completion.
- Provides RTL designers with an efficient, user-friendly experience, offering physical design feedback, localization and categorization of violations, bottleneck analysis and cross-probing between RTL, schematic, and layout.
“Now RTL designers can rapidly access all the physical information needed for PPAC debug without having to wait for implementation, which previously took days or weeks,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “Joules RTL Design Studio gives designers visibility into the challenges when they can still be addressed easily, ultimately speeding time to market. Our early engagements reaffirmed our initial target of up to 5X faster RTL convergence and up to 25% improved QoR.”
Joules RTL Design Studio is part of the broader Cadence digital full flow, which provides customers with a faster path to design closure. The new tool and the broader flow support the company’s Intelligent System Design strategy, enabling system-on-chip (SoC) design excellence. For more information on Joules RTL Design Studio, please visit www.cadence.com/go/joulesrtldspr.
Customer Endorsements
“Our engineers were able to achieve 2-3X better productivity through analysis efficiency, significantly reducing iterations between RTL designers and implementation. Joules RTL Design Studio provides us with a robust and efficient mechanism to find and categorize timing violations based on logical and physical causes as well as bottleneck analysis and cross-probing to RTL, schematic, and layout. Design issues were discovered earlier than they would have been with our previous front-end design process. In conjunction with the complete Cadence digital full flow—Genus Synthesis Solution, Innovus Implementation System, and Tempus Timing Signoff Solution—our design schedules were further reduced. In addition to the design we’re working on currently, we plan to use Joules RTL Design Studio to improve design efficiency with future projects.”
Shunji Katsuki, general manager, SoC System Development Division, Global Development Group, Socionext said “Our RTL design teams focus on creating silicon products that deliver smarter user experiences with more performance and power efficiency. This requires making design decisions based on early estimates of power, performance, area, and congestion. Joules RTL Design Studio’s accurate physical prototyping allows our designers to innovate with confidence, reducing the number of iterations between front- and back-end teams, allowing MediaTek to get its wide variety of differentiated products to market faster.”
Harrison Hsieh, senior general manager of Silicon Product Development, MediaTek stated “Identifying RTL bottlenecks early in the design cycle is critical in IP development and enables quicker updates, higher quality RTL and improved PPA. For Arm specifically, Joules RTL Design Studio can help us identify problem points associated with congestion and deep logic, saving us significant time in finding the root cause.”
Mark Galbraith, vice president of Productivity Engineering, Arm “Due to power density increases in today’s SoCs, design energy efficiency has become even more important. To improve energy efficiency, we made considerable efforts to enhance RTL-level optimization. Now, by leveraging Joules RTL Design Studio from Cadence, we can achieve efficient and accurate power breakdown analysis much earlier in the design phase. The tool’s power prediction capability allows quick RTL optimization iterations so our design team can speed RTL optimization effectively.”
