Abstract
Direct RF sampled systems are evolving to encompass broader capabilities, allowing them to capture a wider bandwidth all in a single Nyquist zone. Sampling from 2 GHz to 18 GHz concurrently enables more sophisticated options to monitor a larger spectrum, without issues of frequency band aliasing. Quadrature interleaving offers a novel solution to expand sampling bandwidth without the complexities of managing double rate clocks, clock inversion, or doubling the data output.
Introduction
Part 1 describes the interleaving objectives, discusses errors creating interleaving artifacts, and introduces the range of 40 GSPS analog-to-digital converter (ADC) options using the AD9084. Part 2 explores the quadrature sampling option, along with a quadrature correction mechanism in detail.
An emerging capability that is enhancing data converter prod- ucts is the significant inclusion of embedded digital signal processor (DSP) cores. A relevant example of showcasing embedded DSP included in modern ADCs is to double the effective sample rate without increasing the back-end digital data rates. Using two ADCs with quadrature inputs and a quadrature correction algorithm, a dual 40 GSPS ADC can be configured to produce four 4 GHz digitally downconverted outputs, monitoring a 2 GHz to 18 GHz bandwidth, within a single multichannel converter IC.
First, direct quadrature sampling is described relative to the more common zero IF (ZIF) architectures. Quadrature errors are acknowledged, along with a description of the embedded digital processing needed for quadrature error correction (QEC). Analog RF front-end components, sampling of ADC data, embedded DSP processing, and final processing of data converter I/Q outputs are used. The measured results show amplitude and phase errors both before and after QEC, and the final measured image rejection demonstrates effective direct quadrature sampling from 2 GHz to 18 GHz. The approach is described for the AD9084 IC, yet is generally extendable to any wideband sampling system.
Quadrature Sampling Principles
A traditional ZIF architecture is shown in Figure 1.1 The architecture creates two IF signals in quadrature (90° out of phase) through a quadrature RF downconverting mixer. In this case, the quadrature is created in the local oscillator (LO) circuitry from two sets of physically separated mixers and LOs, each 90° out of phase. The result is two IF frequencies in quadrature. The ability to resolve whether the RF is above or below the LO frequency is visualized by a phase reversal between the I and Q signals at the LO frequency, as shown in Figure 1. Digital downconverters (DDCs) processing real data converter data streams and creating an I/Q output data stream at a reduced bandwidth centered by a numerically controlled oscillator (NCO) are also enabled by these same principles.
Read the full interview here.
