Breker Verification Systems and Codasip Announce Cooperation

Proven Verification Leaders Collaborate on Open SoC Scenario Validation Standards, Methodologies and Metrics

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San Francisco– Breker Verification Systems and Codasip has announced an extensive technical collaboration to develop and improve rigorous verification processes for common RISC-V SoC scenarios.

The announcement comes as Breker and Codasip demonstrate their RISC-V SoC verification and processor IP solutions at Design Automation Conference (DAC) in Booth #2528 and #1451, respectively, at Moscone West.

As RISC-V processor developments extend more into the application processor space, the requirement for high-quality verification techniques that address common SoC scenarios such as cache coherency, security and power management has become critical. Typically, these processes consist of applying a range of algorithms to drive interleaved test content, a largely ad hoc process. Codasip’s and Breker’s core competencies in verification can be applied to the industry problem at large to establish a prescribed verification flow for SoC verification to increase the state of the art for the good of the entire RISC-V community.

“As the complexity of RISC-V processors for state-of-the-art systems continues to increase, testing the final SoC to ensure perfect operation in all conditions is both complex and essential,” remarks David Kelf, CEO of Breker Verification Systems. “Codasip’s expertise in this area coupled with Breker’s renowned solutions can be combined to provide a framework for SoC scenarios, such as cache coherency testing, that will bring precision and rigor to this increasingly complex challenge.”

“Codasip is building the highest quality RISC-V processors on the market, and an essential element of this to ensure exacting levels of operation in SoCs that make use of these devices,” notes Melaine Facon, Director Codasip Design Centre (France). “We are investing heavily in verification excellence and are delighted to work with Breker for the good of the entire RISC-V community and industry at large.”

Visit Breker and Codasip at DAC

RISC-V SoC verification and processor IP solutions demonstrations in the Breker and Codasip will be available today through Wednesday, July 13, from 10 a.m. until 6 p.m.