Hard Paralleling SiC MOSFET Based Power Modules

By Andre Lenze, David Levett, Ziqing Zheng, Krzysztof Mainka, Infineon Technologies



There are several levels of paralleling power semiconductors. The most common is at the chip level internal to power modules, where to achieve higher current ratings. This is due to the fact, that chips can only be designed with a limited current rating, multiple chips need to be paralleled to reach the required current rating. Paralleling can occur at the individual module level where for example the three legs of a six switch module are paralleled to make a half-bridge module at three times the current rating of the individual legs. It can also take the form of using several individual packages for example TO-247 or modules switching together. This article will focus on the latter example of paralleling.

Hard paralleling IGBT power modules, as anyone who has attempted it knows, is a multi-faceted technical challenge requiring experience in power layout, gate driver design, thermal balancing, statistical analysis, magnetic field effects, and even some intuition. Therefore, a wise engineer will approach the task of paralleling SiC power semiconductors with some trepidation knowing that the faster switching speeds will mean that timing and inductances will be very critical. The goal of this article is to explain the key technical hurdles and share some practical experience of paralleling multiple SiC MOSFET modules.

Motivation for paralleling SiC modules

Perhaps the most fundamental question concerning this topic is to ask why parallel modules? What is the advantage of paralleling two 200 A modules to build up a 400 A module, why not simply use a 400 A part? On the commercial side, in the 1200 V class, IGBT modules are available in multiple current ratings and packages up to 3600 A. For SiC MOSFETs the options at higher currents (>400 A) are much more limited, especially if industry-standard packages or multiple sources are required. In addition, physically smaller packages, which are manufactured in high volumes often, can be produced at a lower cost than mechanically larger lower production volume packages.

However, the main reasons for paralleling modules are technical and these reasons become more important with SiC MOSFETs than with IGBT’s for several reasons:

  • Multiple packages can be spread out on a heatsink and improve cooling. This allows more current to be delivered from what are more expensive SiC MOSFET modules.
  • Larger physical packages have higher inductances in both the power loop and the gate driver circuits due to mechanical spacing and the use of screw terminal connections used to carry the higher currents.
  • Using a large number of chips makes internal symmetrical layout and equalization of gate inductance for all the chips very critical and hard to optimize with packages that have limited terminal options.
  • The two previous points enable faster switching speeds and hence lower switching losses and lower voltage overshoots during turn off to be achieved with these smaller packages.

Some of these points can be illustrated by comparing the same 6 mΩ chip set packaged into two industry-standard modules one PCB based and one a 62mm module as shown in figure 1. It can be seen that the 62mm module has more than twice the loop inductance and more than twice the switching losses of a PCB based low profile package.

Figure 1: Comparison between PCB and screw terminal-based packages with SiC MOSFETs

Paralleling differences between IGBT’s and SiC MOSFETs

On closer examination, despite their fast switching speeds when it comes to paralleling SiC MOSFETs, they have some advantages when compared to IGBTs.

  • SiC MOSFETs typically have a higher RDS(on) positive temperature coefficient, when compared to a Si IGBT VCE sat characteristic. This acts as negative feedback during static current sharing. If one device is taking more current those chips or modules, get hotter increasing the RDS(on) and hence reducing the current. This negative feedback reduces the level of thermal imbalance.
  • Si IGBTs show a large increase in switching losses with increasing temperature and this has a positive feedback effect on temperature imbalance. A hotter chip has higher losses so getting even hotter. SiC MOSFETs show a very small increase in switching losses with temperature significantly reducing this effect.
  • SiC MOSFETs have a softer transconductance curve meaning that small changes in gate voltage, when operating in the gate threshold region, have a smaller effect on drain current than an equivalent Si IGBT. This aids in dynamic current sharing.
  • A statistical analysis of the Infineon trench gate devices shows that in terms of parameter distribution, modules with a higher RDS(on) have lower switching losses, which helps to match losses part to part.

Experience with a Paralleling Test Platform

Figure 2 shows a test platform that was designed and built to evaluate the performance of multiple SiC MOSFET modules operating in parallel. Shown is a power PCB with four 6 mΩ 1200 V SiC MOSFET half-bridge modules connected in parallel. We will consider several aspects of this design platform.

Figure 2: Paralleling test platform

Module internal layout

Paralleling must start with consideration of the module internal power and gate layout. In the case of this module shown in figure 3 and an example of how the internal chip layout and module pinout can be designed to provide equal and symmetrical power and gate driver layout for the multiple chips in parallel. This is achieved while also keeping a low inductance layout switching loop inductance.

Figure 3: Above exemplary internal chip and DCB layout and below exemplary module pinout and schematic for half-bridge topology. Illustrating options for a symmetrical and low inductance layout

In general, the pin grid array of style of PCB based modules allows the flexibility to optimize the layout.

Power PCB Layout

For the power layout, as already shown in figure 3, the module is divided into two symmetrical halves. To match this symmetry the power layout shown in figure 4 was made as a mirror image down the centerline like butterfly wings. This is required to keep equal current sharing among the chips internal to the module. An exact facsimile of the layout was used for each of the four modules to keep current sharing between modules equal. See figure 2. It is also important to keep the external switching loop inductance low and this is achieved by overlapping the DC+ and DC-bus connections with multiple PCB copper planes and using local decoupling capacitors.

Figure 4: Power Stage PCB Layout

Gate driver circuit design

When using a common gate driver circuit for all four modules with multiple gate connections, it is important to reduce any currents flowing in the auxiliary source connection. Figure 5 shows, in a simplified example of two modules, how the auxiliary source connection offers a natural parallel conduction path to the main current path. Some electrons, which we call them “teenager electrons” because they like to take a different path from everyone else, can flow in this auxiliary source parallel path. This current can be large enough to cause gate oscillations and even fuse open the module internal auxiliary bond wires.

Figure 5: Paths for current flow with a common auxiliary source connection

The circuit shown in figure 6 was used to reduce these unwanted circulating currents. It is a combination of a common mode choke, which shows low impedance to normal gate currents where the in and out currents are equal, but high impedance to unwanted source currents flowing only in the source connection. In addition to this, a separate local boost stage was used for each pair of device gate connections. This allows for resistance in the source connection, but, with local capacitors, any current flowing in this path does not affect the gate waveforms. This is not the case if only a simple source resistor is used as any current flowing in that source resistor affects the gate source voltage, which reduces the level of direct control and increases the potential for gate oscillations.

Figure 6: Gate driver circuit

Gate driver PCB layout

The 6 mΩ module, shown in figure 3, has a dual gate source pins and dual power drain and source connection points to reduce inductance and improve current sharing amongst the SiC MOSFET chips internal to the module. The first challenge of the gate layout is to have a symmetrical layout for both pairs of gate source connections. 

This symmetry is achieved by a mezzanine gate driver PCB mounted on top of the power PCB as shown in figure 7.

Figure 7: Mezzanine structure for gate driver PCB

After this is it key to turn on and off the gates of all four modules at the same time. The “tree” structure highlighted in yellow in figure 8 achieves this with low inductance trace pairs gate/source with similar lengths. Also for the local boost stage for each pair of gate course connections the layout was symmetrical as shown top left in orange in figure 8. Measurements showed a worse case timing skew of less than 5nS difference between the gates during switching.

Figure 8: Gate driver PCB tree structure layout


Figure 9 shows the schematic used for the Double Pulse Testing (DPT). It is important to measure the current sharing with the topology set up as a half-bridge so that the current flows and magnetic fields match the final application. In addition, it is required to have the capability to generate synchronous rectifier switching pulses for the complementary device under test with dead times that meet the system dead time requirements.

Figure 9: Double pulse test (DPT) schematic

To measure the drain and source currents, the DC bus PCB traces were laid out with holes on both sides to allow the use of a Rogowski coil. These are shown in figure 10, allowing the measurement of the current in the DC- bus, which is the source current of the lower switch, and the DC+ bus current which is the drain current of the upper device. Also, an allowance was made to be able to measure the output current balance between the two sets of module output pins. Figure 11 shows the Rogowski coil measuring the DC- bus current.

Figure 10. Power module PCB layout and current sense holes

Figure 11: Rogowski coil used to measure lower switch source current

Static Current Sharing

Figure12 shows the source current in the four lower devices during a DPT. Synchronous rectification was used after the first pulse to turn on the upper SiC MOSFET, following the dead time; but, not after the second pulse which allows the current to freewheel through the upper body diode. Current sharing of four matched modules was +/- 3 percent. Note that the current sharing is worse after the second pulse when the MOSFET is not gated and only the body diode is conducting current.

Figure 12: DPT current waveforms for four paralleled modules (50 µs/division and 50 A/division), green Vgs 5 V/division, blue Vds 100V/division

This initial test was done with modules selected to have an RDS(on) variation of less than 2 percent. Tests were also performed with modules with a 7 percent RDS(on) variation and the sharing was only marginally worse at +/- 4 percent. Additional testing at high temperature and switching upper devices showed equally good performance. Figure 13 shows an expanded view of the current waveform in figure 12.

Figure 13. DPT current waveforms for four paralleled modules (50 µs/division and 50 A/division)

Dynamic Current Sharing

Dynamic sharing for both turn on and off waveforms of the lower devices showed excellent sharing as shown in figures 14 and 15. No current oscillations were observed which indicates the devices are sharing current during the turn on and off sequence. Testing at different temperatures, measuring upper devices, and with 7 percent RDS(on) variations all showed similar performance.

Figure 14: DPT turn-off waveforms for four paralleled modules (200 ns/division and 50 A/division), green Vgs 5 V/division, blue Vds 100V/division
Figure 15. DPT turn-on waveforms for four paralleled modules (200 ns/division and 50 A/division), green Vgs 5 V/division, blue Vds 100V/division

Current sharing in lab vs high volume production

So excellent current sharing has been shown in the lab with a very small sample. However, if this design has to be translated into a high volume commercial product, current sharing for randomly selected modules with their normal distribution of electrical parameters must be calculated.

Figure 16: Flow chart for Monte Carlo analysis

The method used for this is referred to as a Monte Carlo analysis named after the famous casino in Monte Carlo. The block diagram for this analysis is shown in figure 16. A set of four modules are selected (each one randomly) from the statistical production spread of RDS(on) and switching losses values. Using these parameters for each module, the current in each module is calculated and the junction temperature is estimated. As the RDS(on) and switching losses are temperature dependent, an iteration is used to calculate the final current and junction temperature of each module. This process can be repeated for say 50,000 sets of randomly selected modules and the normalized distribution of Tj calculated. In this case, the result was a variation at +/- three sigma of +/- 7C. Another wrinkle in the calculation is that there is a cross-correlation between RDS(on) and switching losses Etot where parts with a lower RDS(on) trend to a higher Etot value.


This article has shown that four modules can be paralleled with excellent current sharing in both static and dynamic operating conditions and with a Monte Carlo analysis parts can be selected at random and still achieve good sharing for volume production. Care must be taken with the gate driver auxiliary circulating currents and of course engineers must follow the three most important design rules when paralleling power semiconductors namely symmetry, symmetry, and symmetry.


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