Mobiveil, Inc., a fast-growing supplier of silicon intellectual property (SIP), platforms and IP-enabled design services, today announced successful inter-op verification of its production-proven Enterprise Flash Controller (EFC) Design IP and InPsytech’s ONFI 5.1 PHY IP.
The inter-op verification with Mobiveil’s production-proven, highly flexible and configurable EFC IP and InPsytech’s ONFI-PHY IP achieved unparalleled performance during high-speed data transfers. The inter-op verification was performed using industry-standard verification IP and models.
Additional information of Mobiveil’s EFC design IP and other SIP will be shown at Flash Memory Summit (FMS) Booth #839 August 8-10 at the Santa Clara Convention Center in Santa Clara, Calif. Attendees can stop by the booth to schedule meetings by sending email to ip@mobiveil.com.
“From the moment we kicked off EFC IP development, our IP engineering team focused on delivering high-performance, high-quality IP, which was proven by completing inter-op verification with InPsytech’s ONFI 5.1 PHY,” comments Ravi Thummarukudy, Mobiveil’s CEO. “Engineering groups are now benefiting from availability of an ONFI 5.1 Controller PHY combo to help them accelerate performance of SSD devices used in client and enterprise storage applications.”
“We are thrilled with successful completion and performance achievement of the inter-op verification of our ONFI 5.1 PHY IP with Mobiveil’s EFC IP,” adds Scott Yang, Vice President of InPsytech. “InPsytech’s ONFI 5.1 PHY IP has been adopted by multiple chip design groups across various advanced nodes with speeds reaching up to 3600MT/s with many having proceeded directly to mass production design or tape out.”
Mobiveil’s Enterprise Flash Controller Design IP
Mobiveil’s EFC is used to access external NAND flash for high-speed transactions of multiple pages of read or write data, taking advantage of the pipeline performance of newer enterprise NAND flash devices. Its architecture allows control of ONFI 5.1 and toggle devices with flexible addressing schemes. The controller’s simple architecture takes advantage of the high-performance needs by allowing all device command sequences defined in software.
EFC supports ONFI 5.1 specification with NV-LPDDR4 mode of operation, datapath widths from 16 bits to 256 bits and PHY datapath widths of 16 and 32 bits. Its register transfer level (RTL) code is device independent and works seamlessly with any NAND device and minimal software programming.
Additional features include support for volume addressing, suspend and resume functions, two pass programming, and multi plan and asynchronous plane read commands. One configurable feature is support of the SerDes interface that can be configured to asynchronous with the Flash interface.
Mobiveil’s enterprise Flash controller uses sequences that can be changed according to the needs of the device in the field. It provides high performance for any device including special functions provided by the device. Commands along with sequencing are also software defined to provide the user with control of the device.
The controller supports independent and pipelined interfaces for the command, data, and report phases. It offers the ability for multiple commands queued and in progress to different chip selects or logical unit numbers (LUNs) while simultaneously providing parallel access to all devices attached to the bus. Up to 256 LUNs per channel are supported and a virtual LUNs feature limits the EFC’s gate count based on maximum possible simultaneous LUN operations in the end-user system. The controller has DBI support and can configure warmup cycles through CSR.
Mobiveil’s IP team has more than 20 years of experience developing IP blocks for memory and storage solutions. IP designed by Mobiveil are integrated into hundreds of system-on chip (SoC) designs and shipped to millions of devices worldwide.
Availability
Mobiveil’s Enterprise Flash Controller IP is available for licensing now. It can be targeted to ASIC, FPGA, eASIC and structured ASIC technologies.
