Mobiveil announced availability of COMPEX Compute Express Link (CXL) IP

Highly Configurable CXL Controller IP for a Number of High-Performance Applications, Such as Accelerators, Artificial Intelligence and Machine Learning


MILPITAS, CALIF., February 24, 2020 Mobiveil today announced availability of COMPEX Compute Express Link (CXL) IP. The COMPEX controller is designed to the CXL 1.1 specification and supports Host and Type 1, Type 2 and Type 3 device types. COMPEX also supports dual mode where it can be configured to operate either as a Host or any of the device types. COMPEX supports up to 16 Lanes on a flex bus interface and is compliant with PIPE 5.2 specification. It provides a simple packet-based interface to user logic that supports 128-bit, 256-bit and 512-bit datapath widths and provides a low-latency path for easy integration into a customer ASIC. An implementation can choose one of the datapath widths based on number of lanes and target technology to get low-latency and optimized power consumption from COMPEX controller.

For, COMPEX uses Mobiveil’s PCI-SIG compliant GPEX controller and adds CXL.mem and CXL.cache layers that are highly efficient and configurable for a low-latency coherent path.

COMPEX supports store-and-forward mode in RX direction for and cut-through mode for CXL.mem and CXL.cache traffic. It supports cut-through mode in TX direction for all traffic types (IO, Cache and Mem). It implements RCiEP and CXL DVSEC Device Capability as part of RCiEP configuration space in Device mode and implements RCRB for both Host and Device modes.

“Emerging applications such as artificial intelligence, machine learning and cloud computing are driving demand for high-speed, efficient communication between the CPU and platform enhancements and workload accelerators –– that’s where CXL comes into play,” says Jim Pappas, CXL Consortium™ chairman. “Member companies such as Mobiveil that offer CXL based silicon IP solutions are integral to accelerating adoption of the CXL industry standard and growth of a robust CXL ecosystem.”

“We are committed to provide leading-edge design IP solutions for the CXL specification,” remarks Ravi Thummarukudy, CEO of Mobiveil, Inc. “Our solution is verified for functionality and compliance against Avery Design Systems’ CXL Verification IP. We also provided multiple low-latency user interfaces for each of the traffic types for easy integration of COMPEX IP in to a CXL SoC. The emergence of the CXL standard will enable a number of high-performance applications, such as artificial intelligence, machine learning and data center accelerators.”

Mobiveil’s controller has a simple, configurable and layered architecture independent of application logic, PHYs, implementation tools and, most important, the target technology itself. It allows the user to migrate between standard cell technologies and field-programmable gate arrays (FPGAs). The controller’s flexible backend interface can be integrated into wide range of applications.

The CXL controller architecture optimizes link utilization, latency, reliability, power consumption, and silicon footprint. The controller handles PCI Express ordering rules and implements multiple VCs and associated flow control logic in both directions. The packet-oriented user logic interface also supports PIPE 5-compliant PHYs, and flexible lane ordering and support for lane reversal.

“We are excited to collaborate with Mobiveil to bring total, best-in-class robust pre-validated IP solutions to our customers, and streamline the design and verification process and foster the rapid adoption of the CXL standard,” states Chris Browy, vice president of sales/marketing at Avery. “Mobiveil and Avery are long-term partners and are both respected leaders in SIP and VIP.” Avery provides a complete System Verilog/UVM verification solution including models, protocol checking, and compliance test suites for PCIe 5.0,, CXL.mem and CXL.cache.

The IP team at Mobiveil has more than 15 years of experience of IP development starting with early versions of PCI Express, Serial RapidIO and Ethernet technologies. Since then, Mobiveil developed and productized every generation of these technologies through the latest specifications. The interface IP designed by Mobiveil is integrated in hundreds of system-on-chip (SoC) designs and shipped in millions of devices.


Mobiveil’s CXL 1.1-based COMPEX Controller IP will be available by the end of Q1, 2020. This IP can be targeted to FPGA, eASIC and Structured ASIC technologies. CXL 2.0-based COMPEX controller is targeted to be available in for early Q3, 2020 availability.

Pricing is available on request. More information on Mobiveil’s COMPEX IP is found at the Mobiveil website