Siemens Unveiled Veloce Hardware-Assisted Verification System

This highly cohesive system takes hardware, software and system verification to the next level of intelligent digitalization by streamlining and optimizing verification cycles while helping to reduce verification cost

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PLANO, Texas, – Siemens Digital Industries Software today unveiled its next-generation Veloce hardware-assisted verification system for the rapid verification of highly sophisticated, next-generation integrated circuit (IC) designs. This is the first complete, integrated offering that combines best-in-class virtual platform, hardware emulation, and Field Programmable Gate Array (FPGA) prototyping technologies and paves the way to leverage the latest powerful hardware-assisted verification methodologies.

New products in the Veloce hardware-assisted verification system are:

  • Veloce HYCON (HYbrid CONfigurable) for virtual platform/software-enabled verification. Veloce HYCON delivers innovative technology that allows customers to engineer and deploy complex hybrid emulation systems for their next-generation system-on-chip (SoC) designs.
  • Veloce Strato+, a capacity upgrade to the Veloce Strato hardware emulator. With an industry-leading capacity roadmap that scales up to 15 billion gates, Veloce Strato+ combines the industry’s highest total throughput with its fastest co-model bandwidth and time-to-visibility.
  • Veloce Primo for enterprise-level FPGA prototyping, an internally developed enterprise prototyping solution that combines industry-leading runtime performance with exceptionally fast prototype bring-up.
  • Veloce proFPGA for desktop FPGA prototyping. With a modular approach to capacity, the Veloce proFPGA family of products delivers scalability across a range of capacity requirements.

This highly cohesive system sets a new standard for the future direction of hardware-assisted verification methodologies. The system takes hardware, software and system verification to the next level of intelligent digitalization by streamlining and optimizing verification cycles while helping to reduce verification cost.

This seamless approach to managing verification cycles emphasizes running market-specific, real-world workloads, frameworks, and benchmarks early in the verification cycle for power and performance analysis. This enables customer-built virtual SoC models early in the cycle and the integration to begin running real-world firmware and software on Veloce Strato+ for deep-visibility to the lowest level of hardware. Customers can then move the same design to Veloce Primo to validate the software/hardware interfaces and execute application-level software while running closer to actual system speeds. To make this approach as efficient as possible, Veloce Strato+ and Veloce Primo use the same RTL, the same virtual verification environment, the same transactors and models to maximize the reuse of verification collateral, environment and test content. This is a necessary foundation for a seamless methodology.

“As we enter the new semiconductor mega-cycle, the era of software-centric SoC design requires a dramatic change in functional verification systems to address new requirements,” said Ravi Subramanian, Senior Vice President and General Manager, Siemens EDA. “The introduction of the next-generation Veloce system that addresses these key new requirements is a direct result of the focused investment from Siemens to offer our customers a complete, integrated system with a clear roadmap for the next decade. With today’s announcement, we are establishing a new standard for a system that is capable of supporting the new verification requirements across a diverse set of industries-spanning computing and storage, AI/ML, 5G, networking, and automotive.”

Keys to the expanded Veloce hardware-assisted verification system
Innovation in chip, system, and software design enables Veloce Strato+ to deliver to the capacity roadmap published in 2017 when the Veloce Strato platform was introduced. The innovative design and manufacturing of the Crystal 3+—a new, proprietary 2.5D chip—increases system capacity by 1.5x over the previous Veloce Strato system. This innovation enables Veloce Strato+ to lead in the emulation market with marketing-leading available capacity of 15B gates. This capacity, which is the largest effective capacity available today, is now in use at multiple Veloce Strato+ customers.

“AMD utilizes Veloce Emulation platforms as part of our pre-silicon verification and validation solutions,” said Alex Starr, corporate fellow, Methodology Architect, AMD. “The high-performance designs we create demand scalable, dependable and innovative emulation solutions. We are delighted to have worked with Siemens to pioneer high-capacity Veloce Strato+ system deployment at AMD. Furthermore, we’re excited to see 2nd and 3rd Gen AMD EPYC™ processors qualified for use with Veloce Strato and Veloce Strato+ platforms. The high-performance capabilities of both families of processors bring new levels of productivity to the Veloce ecosystem and its customers, like AMD.”

The Veloce Strato system is also expanding the list of qualified processors by adding the AMD EPYC™ 7003 series processor, starting today. These new processors are fully qualified to run with the Veloce Strato systems as run time hosts and co-model hosts.

Veloce Primo and Veloce proFPGA represent the industry’s most powerful and versatile approach to FPGA prototyping. The enterprise-level FPGA prototyping system, Veloce Primo, simultaneously delivers outstanding performance, with capacity scaling up to 320 FPGAs and a consistent working model with Veloce Strato in terms of software workloads, design models and front-end compilation technology. This fundamental alignment between emulation and prototyping contributes to reducing the cost of verification by leveraging the right tool for the task where the emulation and the prototyping work together as complimentary solutions for a better outcome in the shortest cycle. Veloce Primo also supports both virtual (emulation offload) and in-circuit-emulation (ICE) use models for highest possible performance while maintaining accurate clock ratios in both modes.

“The increasing demand for computing in all industries means time to market is critical,” said Tran Nguyen, senior director of design services, Arm. “The Veloce Primo enterprise FPGA prototyping solution from Siemens helps Arm quickly resolve design issues and achieve verification objectives so that our ecosystem can deliver quality Arm-based SoCs to support the rapid pace of innovation.”

“We are delighted to welcome Siemens to the FPGA prototyping market with their launch of Veloce Primo,” said Hanneke Krekels, senior director, Core Vertical Markets, at Xilinx. “Xilinx has a long-standing relationship with Siemens both as a customer and as a collaboration partner, and we’re excited to provide our recent and industry-leading Virtex UltraScale+ VU19P device enabling scalability and capacity to this new product offering.”

Veloce proFPGA brings a proven, world-class desktop platform to the Veloce hardware-assisted verification system (via an OEM agreement with Pro Design). With a modular approach to capacity, the Veloce proFPGA family of products delivers scalability across a range of capacity requirements – from 40M gates to 800M gates – based on high-end FPGAs including Intel Stratix 10 GX 10M and Virtex UltraScale+ VU19P device.

“The advanced technology found in the proFPGA family delivers many advantages for validating today’s AI/ML, 5G, and data center ASIC designs,” said Gunnar Scholl, CEO of Pro Design. “We are excited to partner with Siemens. Our collective experience, insight and strategy for the FPGA desktop prototyping market is being recognized, and we are excited to accelerate market penetration in this space through the collaboration with Siemens.”

Further information is available on the Internet at www.siemens.com.