Abstract
Part 3 of this article series explains a simple method for designing loop compensation in current-mode controlled switch-mode power supplies. This control architecture is extensively used in power management solutions, including many of ADI’s power products. It enables the use of a simple Type 2 compensation network to design and optimize the supply feedback loop, ensuring rapid transient responses and robust stability margins. This article introduces fundamental loop design concepts, offers clear explanations of the Type 2 compensation network, and examines the role of each compensation component. The loop design process is then streamlined into three straightforward steps. Additionally, the LTpowerCAD design tool further simplifies the loop design and optimization process.
Introduction—Basic Concepts
Switch-mode power supplies are extensively used in modern electronic systems to achieve high efficiency and power density. For less experienced system engineers, power supply loop compensation design optimization can be a critical yet challenging task. Most of ADI’s switch-mode regulators employ current-mode control architecture to achieve high performance and high reliability. For example, Figure 1 shows the basic feedback loop block diagram of a popular current-mode control step-down buck converter.1 This architecture features an inner current sensing loop and an outer output voltage regulation loop. The inner current sense loop forces the inductor current to follow the compensation network output voltage at the ITH node. In this way, conceptually the inductor becomes a current source controlled by the voltage loop error amplifier output V ITH . Consequently, the buck converter power stage including the current loop behaves as a single-pole system at lower frequencies below the current loop bandwidth. Therefore, a simple Type 2 compensation network is adequate to optimize supply loop stabilities and transient performances. The example Type 2 compensation network is shown in Figure 1 as the R TH , C TH , and C THP network on the error op amp output ITH pin.
Figure 2 shows the conceptual power supply loop gain diagram. K REF is the feedback resistor-divider network gain from supply
output V O to the FB pin. A(s) is the voltage loop compensation error amplifier network gain from the FB pin to the ITH pin. G CV (s) is
the power stage transfer function from error amplifier output node V ITH to power supply output voltage Vo, including the inner
current loop. Therefore, the total power supply loop gain T(s) is given by Equation 1:
Switching Power Supply Loop Design and Optimization Goals
An optimized power supply loop should be designed with high loop bandwidth to achieve fast transient response while maintaining sufficient stability margins. Furthermore, for a switching power supply, it is important to attenuate the switching noises in the feedback loop to minimize switching waveform jitters. In summary, here are key supply loop design targets:
- Loop bandwidth (f BW ): While high loop bandwidth is generally desirable for fast transient response, it is practically limited by the switching frequency (f SW ). Typically, the maximum bandwidth is set up to 1/10 or 1/5 of f SW .
- Phase margin: A phase margin greater than 45° is usually required, with a margin greater than 60° phase margin being recommended.
- Gain margin: Gain margin, defined as the gain attenuation where the loop phase is –180°, should be at least 8 dB to 10 dB.
- Switching noise attenuation margin: For a current-mode control switching supply, it is important to attenuate switching noises in the feedback loop to minimize jittering of the switching node waveform. Practically, greater than 8 dB attenuation at f SW /2 is preferred.
Intuitive Understanding of Type 2 Compensation Network
To design and optimize the compensation network, a power supply designer first needs to understand the effect of each compensation R or C value on the loop gain and load transient response. Figure 3 shows the Type 2 compensation network, including a typical transconductance error amplifier (that is, a voltage-controlled current source) with a gain of g m , the amplifier parasitic output resistance R 0 , and the compensation network including R TH , C TH , and C THP . These three key ITH pin R/C components are to adjust the compensation gain A(s) and therefore determine the supply loop gain bandwidth, stability margins, and transient response performances.
