VSORA Unveiled PetaFLOPS Platform to Accelerate L4/L5 Autonomous Driving

Powerful Multi-Core DSP Architecture Provides Flexibility While Eliminating Need for DSP Co-Processors, Hardware Accelerators


PARIS VSORA today unveiled the first PetaFLOPS computational platform to accelerate Level 4 (L4) and Level 5 (L5) autonomous vehicles designs.

The programmable solution, delivered as an IP block called AD1028, combines digital signal processing (DSP) and machine learning (ML) acceleration for the autonomous driving industry. Its powerful multi-core DSP and AI architecture eliminates the need for DSP co-processors and hardware accelerators to provide a level of flexibility never achieved previously. “We are proud to be the first to offer computational power, portability and economy in one device for designing L4 and L5 autonomous vehicles,” remarks Khaled Maalej, CEO and founder of VSORA. “AD1028 is the first in a series of platforms from VSORA to provide global vehicle manufacturers early commercial availability of L4 and L5 functionality.”

Introducing AD1028

While a human driver can still take control of the vehicle in Level 4 autonomy, Level 5 removes entirely the human driver to achieve fully autonomous driving capabilities. The computational requirements to achieve L4 and L5 driving autonomy are daunting.

The modular architecture of AD1028 is well suited to meet the challenging task. With computational power of 1,028 TeraFLOPS or one PetaFLOPS running at 2GHz, AD1028 processes an eight-million pixel images on a Yolo-v3 in less than seven milliseconds (ms) and a full HD image in less than 1.6 ms. It can handle multiple parallel instances of any combination of all types of sensor fusions, including hybrid fusion when the fusion requires signal processing as well as AI functionality. The processing power can be configured by the user without changing the high-level description of the algorithm.

The computational device combines DSP and deep neural network (DNN) engines configured to eliminate the performance bottleneck associated with external memories caused by restricted data-transfer bandwidth. It reduces latency and power consumption by shortening the datapath to and from the memory.

Through an on-chip memory shared between the platform’s DSP and AI sections, AD1028 empowers the user to implement an efficient, low-latency Perception stage, and combine it with the Planning stage on the same device using algorithmic combinations of AI and advanced mathematical formulas.

Implemented on 7-nanometer process technology, the AD1028 logic area measures 35 mm2 and consumes less than 35 watts.

Availability and Pricing

The AD1028 platform is available now. It is the first in a family of products to be introduced through the end of 2020 offering a range of processing power.

Pricing is available upon request.

Email requests for more information about AD1028 or other VSORA Solutions should be sent to press@vsora.com.

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