CacheQ Debuts Heterogeneous Compute Development Environment

Delivers Faster Performance, Reduced Development Time for Processor, FPGA Compute Architectures


LOS GATOS, CALIF. – September 5, 2019 – CacheQ Systems unveiled its QCC Acceleration Platform, a heterogenous compute development environment delivering faster performance and reduced development time for processor and field programmable gate array (FPGA) compute architectures.

“Demand for hardware acceleration beyond x86 is tremendous,” remarks Clay Johnson, chief executive officer and co-founder of CacheQ Systems. “Our goal is to simplify high-performance data center and edge-computing application development. The QCC Acceleration Platform meets that goal and will enable new solutions across a variety of applications, including life sciences, financial trading, government, oil and gas exploration and industrial IoT.”

The QCC Acceleration Platform Advantage

“There are so many FPGA chips on the edge and in custom systems that are not optimally used,” notes Jay Zaveri, general partner at Social Capital and founder of the Discover program. “We believe an Ultravisor that runs code directly on these systems with no complicated hardware design is a critical need for computational infrastructure today – code that runs 50X faster in minutes instead of months. We believe the technology that CacheQ has invented and the stellar team they have could tackle this
really hard problem head on.”

Existing FPGA solutions have evolved over the last 30 years and focus solely on hardware designers, not the needs of software developers. The QCC Acceleration Platform is meant for software developers with limited knowledge of hardware architecture and delivers 100x performance with 15x reduction in development time.

While existing technologies require a variety of tasks to be done by hardware designers with results validated by execution in hardware, the QCC Acceleration Platform’s fully pipelined implementations are complimented with a custom many-port pooled memory architecture. It simplifies processor and FPGA compute architecture design, letting software developers implement applications in days compared to a more typical nine- to 12-month schedule.

Based on the proprietary CacheQ virtual machine (CQVM), the QCC Acceleration Platform is a heterogenous compute development environment that converts serial high-level language (HLL) code into a parallel representation in less than 30 seconds for the most complex designs. It supports code profiling, utilization estimates, performance simulation, memory configuration and partitioning across a variety of compute engine processors, including x86, Arm and RISC-V, and FPGAs, prior to generating a compute executable.

Features include a development environment with uniform drivers, protected containers and support for multiple boards from multiple vendors. Its design analysis offers profiling, performance simulation and memory activity reporting. Its optimization capability adds code unrolling, user-driven memory configuration, and automatic and user-guided partitioning. The FPGA implementation includes a resource estimator, pre-configured shells, multiple boards and parts, and implementation tool automation. The memory implementation supports automatic integration, multi-port/multi-access and stripping.

The QCC Acceleration Platform is shipping now in limited volume, with general availability in Q4 2019. The initial release supports FPGA accelerator boards from Alpha Data, Bittware and Xilinx. Support for processor and FPGA system on chip (SoC) boards will be available later in the year.