Cadence Design Systems is helping industry players overcome the chip design bottleneck. Today’s chip design teams could spend 5-7 days per iteration to meet chip-level signoff timing and power requirements. This creates a significant bottleneck for designers who are working to get next-generation applications in a timely manner. TimesTech interacted with Brandon Bautz, Senior Group Director, Product Management in the Digital & Signoff Group at Cadence to know about how its solution automates and accelerates the complete design closure cycle from weeks to overnight.
Read the ful interview here:
TimesTech: Tell us about the products and services of Cadence Design Systems.
Brandon: Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare.
TimesTech: What are the challenges that come with growing design sizes and complexity?
Brandon: As designs grow in size and complexity, EDA tools and methodologies have failed to keep pace. Furthermore, to meet aggressive production schedules, designers demand an efficient, predictable path to achieving their power, performance, and area (PPA) goals.
To solve this, we’ve addressed the block-level closure challenge through the Cadence Innovus Implementation System and Cadence Cerebrus Intelligent Chip Explorer. In a similar fashion, we’re proud to introduce the Cadence Certus Closure Solution to provide a complementary solution to full-chip closure.
TimesTech: How is the Cadence Certus Closure Solution providing customers with a first-of-its-kind fully automated environment?
Brandon: The Cadence Certus Solution is built from the ground up with a focus on improving designer productivity. The solution achieves this by automating every step of the closure process—from chip-level timing analysis to block-level optimization and all the way through detailed routing, metal fill and parasitic re-extraction. Furthermore, the Certus Closure Solution is launched by a single designer and driven from a single cockpit interface, which is a very different approach from traditional design closure methods that require teams of engineers to individually run a collection of point tools. We call this approach empowered collaboration, and it is a key factor in driving up to a 10X improved productivity benefit.
TimesTech: How is the company supporting design optimization and signoff with unlimited capacity?
Brandon: By employing massively parallel technology, the Certus Closure Solution distributes the concurrent optimization and analysis workloads providing a significant capacity increase.
TimesTech: How does this cloud-ready solution advance emerging design areas including hyperscale computing, 5G communications, mobile, automotive, and networking?
Brandon: All of the Cadence Certus Closure Solution’s benefits—improved productivity, empowered collaboration and optimal PPA—contribute to advancing state-of-the-art chip design. At the end of the day, the Cadence Certus Closure Solution’s distribution, integration and automation capabilities significantly accelerate the full-chip closure cycle.
TimesTech: What are Cadence’s plans and focus areas?
Brandon: We can’t discuss future plans and roadmaps, but we are focused on delivering optimal design software, hardware, and IP so that customers can stay in front of the industry’s most pressing design requirements.
