The Cadence 3D-IC solution provides 3D design planning, implementation, and system analysis in a single, unified cockpit. It enables hardware and software co-verification and full-system power analysis using emulation and prototyping and chiplet-based PHY IP for connectivity with power, performance, and area (PPA) optimized for latency, bandwidth, and power. TimesTech interated with Vijayakumar C Patil, group director, Application Engineering, System Design and Analysis, Cadence India to learn about Cadence offerings, challenges that designer face, Hetrogenous integration and much more.
Read the full interview here:
TimesTech: How is Cadence’s 3D-IC offering a comprehensive solution for Chiplet based designs?
Vijayakumar: The Cadence Integrity 3D-IC platform is built on the infrastructure of Cadence’s leading Innovus Digital Implementation System, connecting all critical design flows required for chiplet-based 3D-IC design. The platform is the industry’s only complete offering that combines system planning, packaging, and system-level analysis in a single cockpit. It enables chiplet-based system analysis along with co-design via the Cadence Virtuoso and Allegro design platforms for analog and package implementation. Key capabilities of the offering include integrated 3D design planning and implementation and the ability to perform early thermal, power, and timing analysis and system-driven power, performance, and area (PPA).
TimesTech: Why solely relying on process shrink has now became unviable?
Vijayakumar: With the slowdown in Moore’s law, we need a technical and economical path forward to cope with the massive proliferation of emerging technologies as well as requirements for high-performance, high-bandwidth, pixel-heavy, and low-latency computing. Taking the lower node path alone has the following challenges: reticle limits in manufacturing, chips becoming larger, increasingly defective chips with lower yield, IR drop, timing slack, power leakage, and more. From an economic perspective, the cost per transistor goes up exponentially. Therefore, the path to 3D-ICs originates from the need to strike a balance between technical challenges and the business economy.
TimesTech: What are the challenges designers face when they transition from single monolithic devices to multi-chiplet architectures?
Vijayakumar: The designers of single monolithic chips must address the challenges of interconnect design from one chiplet to another. This is not just about static timing analysis (STA) any longer. Multi-chip power, cross-die timing, accurate and fast modelling of interconnects and compliance are crucial capabilities that ensure signal integrity through interconnects. Thermal analysis, which includes reducing possible heat generation and ensuring cooling across chiplets, will be another growing challenge. Companies must train designers on cross-domain design concepts and flows— system, package, and IC design.
TimesTech: What is Heterogeneous Integration?
Vijayakumar: One of the biggest advantages of 3D/2.5D chiplet-based design is the flexibility of choosing and bringing different technology nodes together to achieve much larger IC design goals. For example, designing or re-using memory or analog chiplets at older and mature technology nodes, designing CPUs or GPUs using the latest advanced process nodes, creating IO designs at moderate advanced nodes can all be integrated with 3D die-stacking, silicon interposers, and a variety of advanced packaging methods, otherwise known as Heterogeneous Integration.
TimesTech: What are the challenges to EDA tools in chiplet-based approach?
Vijayakumar: The Heterogenous Integration of chiplets requires the convergence of IC design tools and system design tools. For example, if you had 8 tools in a flow, now you are integrating 15 tools in a flow. Both 3D and side-by-side chiplet stacking require design planning and connectivity across chiplets, with a huge number of bumps per chiplet. It also requires early thermal, signal, and power analysis flows. There are many variables to consider when tuning chiplets, and it is necessary to properly address these variables. In short, tools need to facilitate solutions that can handle the vast, multi-dimensional matrix of possibilities. Cadence Integrity 3D-IC is well-positioned to meet the industry’s most complex requirements.
