For the 43rd consecutive year delivering a unique convergence of microelectronics technology and circuits in one venue, Symposium on VLSI Technology & Circuits will resume as an in-person event in Kyoto, Japan on June 11–16, 2023. The six-day event will take place at the Rihga Royal Hotel Kyoto to showcase the theme of “Rebooting Technology and Circuits for a Sustainable Future.” The Symposium will feature advanced VLSI technology developments, innovative circuit designs, and the applications they enable, such as artificial intelligence, machine learning, IoT, wearable/implantable biomedical devices, big data, cloud/edge computing, and augmented/virtual reality (AR/VR).
The weeklong Symposium is the premier global venue that promotes synergies between technologists and designers on today’s applications and future breakthroughs. In addition to the technical presentations, the Symposium program will feature a demonstration session, joint focus sessions, evening panels, short courses, workshops, and a special forum.
Plenary Sessions:
• “Multi-Chiplet Heterogeneous Integration Packaging for Semiconductor System Scaling” by Suraya Bhattacharya, Director, System-in-Package, A*STAR, IME
Over the past decade, diverse system requirements from a broad range of markets have driven the industry to embrace advanced packaging to heterogeneously integrate multiple chiplets as a key new toolbox for System-in-Package scaling. Dr. Bhattacharya will provide an overview of multi-chiplet heterogeneous integration packaging platforms to address system scaling needs in the coming decades.
• “Searching for Nonlinearity: Scaling Limits in NAND Flash” by Siva Sivaram, President, Western Digital
In this talk, Dr. Sivaram will show that achieving higher bit growth in NAND Flash memory through incessant 3D-stacking of more layers results in sub-linear cost reduction. Wafer bonding technology can disruptively decouple the memory array from complex logic circuits, allowing new integration of high-speed logic with the memory layers, and shortening manufacturing cycle times. This technology frees the industry from one-size-fits-all NAND dies to customized solutions for various applications and system-level savings.
• “Quantum Computing from Hype to Game Changer” by Hiroyuki Mizuno, Distinguished Researcher, Hitachi, Ltd.
Quantum computing is increasingly considered hype as its benefit to the consumer remains unrealized despite widespread investment and investigation. CMOS annealing technology attempts to provide a stop gap solution. This talk introduces the top-down approach that takes full advantage of existing semiconductor technologies and notable developments including the “shuttling qubit” to reach the next milestone to develop silicon quantum computers – qubit operation in a scalable qubit array structure.
• “A Six-Word Story on the Future of VLSI: AI-Driven, Software-Defined, and Uncomfortably Exciting” by Partha Ranganathan, Vice President, Technical Fellow, Google
The AI revolution, cloud, and smart edge are all accelerating the demand for computing, yet Moore’s Law is slowing down. This is constantly challenging traditional assumptions around cheaper and more energy-efficient systems and resulting in a significant and growing supply-demand gap for future computing systems. In this talk, Dr. Ranganathan discusses how to rethink and design future hardware and presents two broad themes – efficient hardware design through custom silicon accelerators and efficient hardware utilization through software-defined systems design.
Focus Sessions:
Two technology focus sessions will be held: “BEOL/Backside Power Distribution Network (BSPDN)” and “Future Memory Directions.” In addition, there will be four joint focus sessions covering both circuits and technology novelty and interest: “New Computing,” “AR/VR/MR Metaverse,” “Automotive and Aerospace,” and “3D System Integration.”
