Breker Unveils The Breker Integrity FASTApps Portfolio

Automated Test Generation Verification IP Elements Focus on Difficult Scenarios for Broad Range of Processor Cores and SoCs


SAN JOSE, CALIF.- Breker Verification Systems unveiled the Breker Integrity FASTApps Portfolio, a library of automated test generation intellectual property (IP) elements targeting difficult-to-verify processor core and system-on-chip (SoC) scenarios.

The FASTApps provide commercial-grade, high-coverage verification for RISC-V processor cores and the SoC platforms that use them.

“The RISC-V Open ISA concept, while powerful, introduces verification challenges to engineering teams unfamiliar with processor complexities,” observes David Kelf, Breker’s CEO, an active RISC-V Consortium member involved with a public effort to improve RISC-V verification methodologies. “By automating test content generation, Breker’s years of verification experience can be encapsulated and applied across many projects, driving high test coverage with a minimal level of effort.”

Breker’s new Integrity FASTApps, ideal for the verification of processors based on the RISC-V Open Instruction Set Architecture (ISA) provide specific test sets for both processor core integrity and the System-on-Chip (SoC) that encompass these cores.

The Processor Core Integrity FASTApps include commonplace, but hard-to-verify scenarios such as load store integrity, random instruction testing, register-to-register hazards, conditionals and branches, exceptions, async. interrupts, privilege level switching, core security, exception testing (memory protection and machine-code integrity), virtual memory/paging and core coherency.

In addition, the SoC Integrity FASTApps include random memory and register tests, system interrupt testing (external, timing and software interrupts), multi-core execution, memory ordering, atomic operations, system coherency, system paging and memory management unit (MMU) operations, system security and power management.

Also available are apps for end-to-end multi-IP SoC testing and early firmware testing for RISC-V.

The FASTApps make full use of the Breker Test Suite Synthesis technology. Features include seamless portability across the entire verification flow and execution platforms, coverage-driven and pre-execution randomization for enhanced use models, powerful debug and performance profiling capability, and concurrent test set. They integrate fully with the Breker TrekApps such as the system coherency, security, power domain, networking and other system verification IP tests for fully comprehensive SoC and core-level verification.

Availability and Pricing

The Breker Integrity FASTApps for RISC-V as well as Arm and X86 based systems are available today.

Pricing is available upon request. Special introductory pricing applies to the FASTApps.

For more information, visit the Breker website or email [email protected].

Breker at the RISC-V Summit

Breker executives and technical staff will be part of the RISC-V Summit program held Tuesday, December 13, and Wednesday, December 14, at the San Jose Convention McEnery Center in San Jose, Calif.

John Sotiropoulos, principal engineer at Breker, will present “The New Verification Ecosystem that Supports RISC-V Verification for all Adopters” with Lee Moore, consulting engineer at Imperas Software, December 13 at 4:20 p.m. P.S. T.

Adnan Hamid, Breker’s CTO, will address “RISC-V SoC and Processor Integrity: Dealing with Unique RISC-V Integrity Issues” December 14 at 12:10 p.m. P.S.T.

Send email to to arrange a meeting.